Quantum Matter Seminar

High-quality superconducting qubits are a prerequisite for achieving scalable and fault-tolerant quantum computing. Realizing such qubits requires a holistic approach that integrates materials engineering, device fabrication, and system-level measurement to identify and suppress dominant loss and noise mechanisms. To this end, we present our experimental efforts toward improving superconducting qubit performance from fabrication to system-level validation. On the fabrication side, we develop a wafer-scale processing flow designed to reduce metal–substrate loss, enabling a peak maximum energy relaxation times (T₁) of up to 529 μs. This approach is inherently scalable and compatible with standardized semiconductor manufacturing, providing a viable pathway toward large-scale quantum processing units (QPUs).

In addition, we further demonstrate that optimization of the measurement environment plays an equally critical role in qubit performance. By suppressing infrared radiation and enhancing electromagnetic shielding, the average qubit T₁ of a multi-qubit QPU is improved from 185 μs to 276 μs. In parallel, the qubit temperature is reduced from 61 mK to 18 mK, accompanied by a substantial decrease in quasiparticle density and a reduction of the parity-switching rate to 0.3 Hz.

These developments are enabled by two recently established platforms in the RCCI, Academia Sinica, Taiwan: the Quantum Chip Fabrication Space (QC-Fab), which provides automated wafer-scale fabrication with high reproducibility, and the Quantum Computing Test Space (QC-Test), which integrates cryogenic hardware, control electronics, and data-driven calibration into a programmable system-level modular testbed. Together, these platforms support rapid iteration, hardware–software co-design, and physics-driven AI-enhanced optimization of superconducting qubits and quantum chips.