EE Devices Seminar

The generation of high-purity clock sources is becoming more crucial in today's communication systems. With the advent of advanced communication systems such as 5G wireless radios and ultra high-speed wireline transceivers, the required clock jitter is now below 50 fs. While recent PLLs have achieved such a jitter specification with a power consumption of just a few mW, they are typically tested with ultra-low noise XOs consuming 100s to 1000s mW, overlooking holistic optimization. This talk discusses two PLL topologies that actively optimize the noise and power of the entire frequency generation and synthesis chain.